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CDB43L22
3.3
SPDIF In to Mono Speaker Out
The CS43L22’s mono differential PWM speaker output performance can be tested by loading the “SPDIF
In to Mono Speaker Out” quick setup file provided with the software package. The script configures the
digital clock and data signal routing on the board as shown in Figure 2 .
Stereo output jacks J6 and J18 can be used to monitor filtered PWM output for measurement purposes. The
figure shows how a real speaker or a speaker model should attach to the binding posts during performace
tests. Please note how ONLY the tip from the stereo jacks is used to attach the mono differential channel
to the measurement device. Digital S/PDIF input can be provided on the optical (OPT2) or RCA (J68) jacks.
Refer to Section 4 on page 11 for details on software configuration.
CS43L22
MCLK
LRCK
FPGA
CS8416
S/PDIF Rx
RX.RMCK
RX.LRCK
SCLK
SDIN
RX.SCLK
RX.SDOUT
(MASTER)
S/PDIF
IN
(SLAVE)
J6
+
+
Spkr A
Pin 4 – SPKOUTA+
Pin 6 – SPKOUTA+
J15
15 μH
Measure -
Pin 7 – SPKOUTA-
Pin 9 – SPKOUTA-
J19
Spkr B
4 Ω
15 μH
Test Load
OR
Real
Speaker
Load
ment
Device
-
-
J18
Figure 3. SPDIF In to Mono Speaker Out
Table 3 shows the expected performance characteristics one should expect when using the CDB43L22
for SPDIF In to Mono Speaker Out measurements.
Plot
Location
THD+N vs. Output Power- S/PDIF In to Speaker Out Figure 30 on page 30
Table 3. SPDIF In to Mono Speaker Out Performance Plots
10
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